In the EEPROM art, it has long been sought to shrink the cell size in order to pack the cells more efficiently onto an integrated circuit chip. U.S. Pat. No. 5,041,886 illustrates an EEPROM cell for medium density (128K bits) in which a stacked floating gate-control gate system has an adjacent select gate that is formed from a polysilicon sidewall that is formed after both the floating gate and control gates are in place. This has the known advantage of reducing the size of the cell area because the sidewall will have a smaller area than the conventional stacked array. In this patent, the select gate and the control gate are controlled by the same word line.
an article by Yamauchi et al in the IEDM 91-319 entitled A 5 V-Only Virtual Ground Flash Cell with an Auxiliary Gate for High Density and High Speed Operation discloses an EEPROM having a planar select gate adjacent to a sidewall floating gate.